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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. february 2013 doc id 022952 rev 2 1/88 1 VD5377 ultra-low power motion sensor for optical finger navigation (ofn) datasheet - preliminary data features ? ultra-low power performance and high speed/high accuracy mo tion detection (up to 28 in/s @ 4000 f/s) ? manual or automatic power management options ? very low quiescent and operating current modes for battery life saving ? fully integrated solution: internal oscillator and led driver ? i 2 c interface with fast polling rates for high-end applications (report rate up to 1 per ms). ? user-selectable i 2 c address (default i 2 c address is 0xa6) ? cpi programmable up to 3,200 cpi ? fully automatic exposure control (aec) applications ? smart phones ? laptop/netbook pcs ? media players ? gps devices ? remote controls for home entertainment equipment description the VD5377 is an ultra-low power, single-chip controller ic containing all the functions necessary for optical joysticks/optical finger navigation modules enabling improved mobile experience and longer battery life. this device is cost and performance optimized for optical finger navigation applications and includes special features to ensure optimum performance even in bright sunlight. www.st.com
contents VD5377 2/88 doc id 022952 rev 2 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 VD5377 enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 floor plan changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 silicon specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 silicon thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 die size and optical center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 pad opening sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.5 bond pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 cursor orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 manual power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 automatic power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 i/o description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 i2c_sel[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 led_out (tracking led) and gpio0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 motion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 feature count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 minimum features threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 x/y scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 automatic exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
doc id 022952 rev 2 3/88 VD5377 contents 6.5 5 x 5 high pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6 sunlight timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.7 automatic/manual frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 auto-movement filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 adaptive cpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 backled[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3.1 pwm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 basic start-up information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1 register override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.2 recommended start-up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 reading x/y motion data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.4 switching between automatic mode and manual mode . . . . . . . . . . . . . . 51 8.5 revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.6 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 image capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 i 2 c image capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.1 step-by-step procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2 fast capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2 digital i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3 i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.3 message interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.4 type of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.4.1 single location, single data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
contents VD5377 4/88 doc id 022952 rev 2 11.4.2 single location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.4.3 multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.4.4 multiple location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12 i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
doc id 022952 rev 2 5/88 VD5377 list of tables list of tables table 1. technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. die size and optical center comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. die size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. optical center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. pad openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. bond pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. typical power consumption - manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. manual mode timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. typical power consumption - automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. automatic mode timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. user-selectable i 2 c addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. control register to dynamically configure device i 2 c address . . . . . . . . . . . . . . . . . . . . . . 24 table 14. control register for led_out and gpio0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. truth-table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. control register for motion pin polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. features and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19. 5x5 high-pass filter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 20. sunlight dmib timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 21. adaptive frame rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 22. modified exposure limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. motion threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 24. auto-movement filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 25. adaptive cpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 26. backled control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 27. analog_ctrl2 recommended setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 table 28. start-up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. x/y motion data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 30. major/minor revision registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. i2c frame dump registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 33. fast capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 34. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. digital io electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 36. i2c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 37. register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 38. i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 39. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 40. delivery formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 41. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
list of figures VD5377 6/88 doc id 022952 rev 2 list of figures figure 1. VD5377 simplified system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. VD5377 bond pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. vtop supply (using in ternal regulator). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. 1.8 v direct supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. VD5377 default xy orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. VD5377 power management modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. manual power mode flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 8. manual power mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. automatic power mode flow diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. automatic power mode timing diagram (use_st andby_pin=1) . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. led drive options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. led control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. typical configuration of gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. motion behavior at po wer-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. in automatic mode th e standby pin functions as i2c enable if use_standby_pin is selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16. automatic exposure algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 17. adaptive cpi algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. backled configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. pwm operation: three independent pwm channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 20. reading x/y motion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 21. accessing low power standby from automatic power mode. . . . . . . . . . . . . . . . . . . . . . . . 51 figure 22. automatic mode to low power standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 23. i2c frame dump timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24. flow chart procedure for i2c fram e dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 25. i2c frame dump output in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 26. fast capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 27. i2c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 28. serial interface data transfer pr otocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 29. VD5377 serial interface address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 30. single location, single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 31. single read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 32. multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 33. multiple location read: reading motion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
doc id 022952 rev 2 7/88 VD5377 overview 1 overview the VD5377 is an ultra-low power, single-chip controller ic containing all the functions necessary for optical joysticks/optical finger navigation modules. it incorporates a 20 x 20, 30.4 m pixel imaging array supporting frame rates up to 4 k frames/s capable of detecting and tracking motion at up to 28 inches/s with high accuracy and low drift. maximum velocity is calculated as follows: maximum velocity = (pixel size/lens magnification) x max frame rate x max.displacement per frame for example: 0.5 magnification = (30 m/0.5) x 4000 f/s x 3 pixels = 0.72 m/s (28 inches/s) figure 1 shows a simplified block diagram of a typical optical navigation system. communication with the device is over a 400 khz i 2 c serial link (i 2 c address is user- selectable). the motion sig nal is asserted when the vd537 7 senses motion and motion x/y data is accessed over the i 2 c link. the user can choose between automatic power management mode, where the device will automatically go in to low power hibernation if no motion is detected or manual power management mode where there is a choice of two low power states: standby or powerdown. the external navigation led driver is fully integrated in the device, supporting drive currents up to 14 ma. where higher power is required, an external driver can be used. figure 1. VD5377 simplified system block diagram ir led led_out 2.2 to 3.0v VD5377 i2c motion powerdown standby host mcu
overview VD5377 8/88 doc id 022952 rev 2 1.1 technical specification 1.2 VD5377 enhancements the VD5377 has been optimized for optical fi nger navigation (ofn) applications. for applications migrating from the previous vd5 376 device, the following list highlights the key differences: ? optimized floor plan for improved module design ? enhanced automatic power management mo de: fully programmable sleep and wake- up intervals ? ultra-low powerdown mode (<1 a) ? user-selectable i 2 c addresses with the option to crea te custom start-up configurations ? programmable polarity on external motion signal ? power-on reset (por) functi on gated on motion signal ? unique backlight controller: three pwm controlled led drive outputs (10 ma) ? enhanced performance in high ambient light conditions ? new filter added to aid navigation in low contrast images ? increased led on-time for greater dynamic range ? simplified support circuit: rbin and cosc components now integrated ? smaller external capacitor on vreg (220 nf) ? improved i 2 c frame capture table 1. technical specification feature detail resolution programmable up to 3200 cpi pixel size 30.4 m array size 20 x 20 pixels frame rate up to 4 kf/s (auto or manual) tracking performance up to 720 mm/s (28 in/s) low drift, high accuracy supply voltage 2.2 v to 3.0 v using internal regulator or 1.8 v direct drive operating temperature -20c to 70c
doc id 022952 rev 2 9/88 VD5377 overview 1.3 floor plan changes table 2. die size and optical center comparison conditions VD5377 vd5376 x (m) y (m) x (m) y (m) die size including seal 1794 1758 1800 1832 including scribe (step & repeat) 1894 1858 1900 1932 optical center relative to die center -83 +447 -91 +319
silicon specification VD5377 10/88 doc id 022952 rev 2 2 silicon specification this chapter contains physical die information. 2.1 silicon thickness standard silicon thi ckness is 180 m (see table 40: delivery formats on page 86 ). 2.2 die size and optical center all dimensions and all coordinates are referenced to the origin at die center. 2.3 pad opening sizes minimum bond pad pitch: 138 m. table 3. die size conditions x size (m) y size (m) including seal 1794 1758 including scribe (step and repeat) 1894 1858 table 4. optical center parameter x (m) y (m) die center 0 0 array center -83 +447 table 5. pad openings x (m) y (m) size 86.4 86.4
doc id 022952 rev 2 11/88 VD5377 silicon specification 2.4 device pinout figure 2 shows the bond pad layout and table 6 provides the bond pad coordinates. all dimensions are in microns. figure 2. VD5377 bond pad layout i2c_sel0 i2c_sel1 i2c_sel2 led_out dvss backled0 backled1 backled2 dvdd gpio0 motion test_clk sda (0,19) (19,19) (0,0) (19,0) 2 1 3 4 5 6 7 8 9 19 20 22 23 24 scl not to scale imaging array array centre die centre(0,0) 608 m 608 m 10 dvss 11 dvreg vtop por_test powerdown dvss 18 17 16 14 13 avss 25 26 avdd dvss 21 12 15 dvdd dvss standby 1st pixel (-83, +447) first pixel indicates start of readout for image streaming.
silicon specification VD5377 12/88 doc id 022952 rev 2 2.5 bond pad coordinates all dimensions are in microns. bond pad coordinates correspond to the bond pad centers referenced to the die center. table 6. bond pad coordinates pad # pad name x co-ordinate y co-ordinate 1 dvss -827.6 792.7 2 i2c_sel0 -827.6 515.6 3 i2c_sel1 -827.6 378.0 4 i2c_sel2 -827.6 240.3 5 led_out -827.6 102.6 6 dvss -827.6 -35.0 7 dvdd -827.6 -218.8 8 backled0 -827.6 -356.4 9 backled1 -827.6 -494.1 10 backled2 -827.6 -631.8 11 dvss -649.8 -810.1 12 dvdd -511.4 -810.1 13 powerdown -317.5 -810.1 14 por_test -213.8 -810.1 15 vtop -110.1 -810.1 16 standby 28.3 -810.1 17 dvreg 470.1 -810.1 18 dvss 649.6 -810.1 19 gpio0 827.6 -632.3 20 motion 827.6 -484.3 21 dvss 827.6 -336.1 22 test_clk 827.6 -187.5 23 sda 827.6 -10.3 24 scl 827.6 145.4 25 avss 827.6 556.0 26 avdd 827.6 733.4
doc id 022952 rev 2 13/88 VD5377 application schematics 3 application schematics there are two power configuratio ns for the VD5377: a 2.2 v to 3.0 v external supply utilizing the device?s internal 1.8 v regulator or dire ct drive using an externally regulated 1.8 v supply. typical application schematics ar e shown for both configurations in figure 3 and figure 4 . the internal 1.8 v core regulator requires a minimum 220 nf decoupling capacitor. larger values may increase the minimum power down ti me which is required to guarantee a proper reset of the device. figure 3. vtop supply (using internal regulator) standby powerdown vtop scl sda motion gnd optional i 2 c address navigation led nc 220 nf nc 1.8v 1.8v i2c_sel0 i2c_sel1 i2c_sel2 led_out dvss backled0 backled1 backled2 dvdd gpio0 motion test_clk sda 2 1 3 4 5 6 7 8 9 19 20 22 23 24 scl 10 dvss 11 dvreg vtop por_test powerdown dvss 18 17 16 14 13 avss 25 26 avdd dvss 21 12 15 dvdd dvss standby VD5377
application schematics VD5377 14/88 doc id 022952 rev 2 figure 4. 1.8 v direct supply note: in a 1.8 v direct drive configuration, the powerdown pin should be connected to 1.8 v to ensure the internal regula tor is switched off to minimize power consumption. 3.1 signal descriptions standby vled scl sda motion i2c_sel0 i2c_sel1 i2c_sel2 led_out dvss backled0 backled1 backled2 dvdd gpio0 motion test_clk sda 2 1 3 4 5 6 7 8 9 19 20 22 23 24 scl 10 dvss 11 dvreg vtop por_test powerdown dvss 18 17 16 14 13 avss 25 26 avdd dvss 21 12 15 dvdd dvss standby VD5377 nc nc 1.8v 1.8v 1.8v optional i 2 c address navigation led 220 nf gnd table 7. signal descriptions pad # signal name type description 1 dvss supply digital ground 2 i2c_sel0 1.8v digital input i 2 c address select input. 5 v tolerant inputs with int egrated pull-down resistor. if unconnected default address is 0xa6. (pads have internal 35 kohm pu ll-down resistors. if connected to vdd, the pull-down resistor is disconnected after the internal microcontroller boot sequence is completed to reduce power consumption). 3 i2c_sel1 1.8v digital input 4 i2c_sel2 1.8v digital input 5 led_out current dac output navigation led drive pad. constant current sink set by internal dac. maximum setting 14 ma. for external led driver use gpio0. 6 dvss supply digital ground 7 dvdd supply 1.8 v digital supply
doc id 022952 rev 2 15/88 VD5377 application schematics 8 backled0 1.8v digital i/o backlight led driver (4 ma, open-drain). 5 v tolerant. if unused, connect to dvss. 9 backled1 1.8v digital i/o backlight led driver (4 ma, open-drain). 5 v tolerant. if unused, connect to dvss. 10 backled2 1.8v digital i/o backlight led driver (4 ma, open-drain). 5 v tolerant. if unused, connect to dvss. 11 dvss supply digital ground 12 dvdd supply 1.8 v digital supply 13 powerdown analog input active high. this disables the internal 1.8 v core regulator. input switching level is 0.8 v to be compatible with 1.8 v or 2.8 v signal. 14 por_test - no connect 15 vtop supply internal 1.8 v regulator supply input: ? 2.2 to 3.0 v for internal regulator configuration ? 1.8 v in direct drive mode. 16 standby 1.8v digital input if use_standby_pin register is selected (register 0x5 bit 4): ? in manual mode standby = 1 puts the device in low power mode ? in auto mode standby = 1 disables i 2 c otherwise, connect to dvss if not used. this pad is 5 v tolerant. 17 dvreg supply 1.8v internal regulator output. connect to dvdd and avdd supplies. requires a 220 nf capacitor to dvss. 18 dvss supply digital ground 19 gpio0 3.0v digital i/o external led drive control signal or general purpose i/o. referenced to vtop. this pad is 5 v tolerant. 20 motion 3.0v digital output motion detection flag. configurable as push/pull or open-drain. active high or low (programmable polarity). referenced to vtop. this pad is 5 v tolerant. 21 dvss supply digital ground 22 test_clk - no connect 23 sda 1.8v digital i/o i 2 c bidirectional data (open-drain). this pad is 5 v tolerant. 24 scl 1.8v digital input i 2 c clock. this pad is 5 v tolerant. 25 avss supply analog ground 26 avdd supply 1.8 v analog supply table 7. signal descriptions (continued) pad # signal name type description
application schematics VD5377 16/88 doc id 022952 rev 2 3.2 cursor orientation figure 5 shows the direction of positiv e motion vectors relative to silicon orientation with the default power-up register settings: parameters _2 (0x27) = 0x08 that is, invert_x = 0, invert_y = 0 and swap_xy = 1. an imaging lens is assumed but not shown. the direction of x/y motion can be reversed or swapped by writing to register 0x27 allowing preferred cursor movement from any die orientation. figure 5. VD5377 default xy orientation y+ x+ pad 1 pixel array imaging lens not shown
doc id 022952 rev 2 17/88 VD5377 system overview 4 system overview the VD5377 operates in one of two power management modes: manual or automatic (see figure 6 ). after initial mcu boot the device enters the sw stby state and waits for configuration from the hos t. when configured, the devi ce enters manual run or automatic run mode. ? manual power management mode is the simp lest mode where the host initializes the device which then remains in manual r un mode until it receives a command to change mode (either an i 2 c command to return to the sw stby state or a low power state using the powerdown or standby pin). ? automatic power management mode is an intelligent, power efficient mode where the device automatically switches to low power mode depending on motion activity. when initialized, the device will continue to operate au tonomously minimizing power consumption and host cpu overhead. figure 6. VD5377 power management modes mcu boot sw stby manual host_config_done = 1 automatic = 0 host_config_done = 1 automatic = 1 host_config_done=0 automatic power up run run
system overview VD5377 18/88 doc id 022952 rev 2 4.1 manual power management manual power mode is the basic mode of th e VD5377. after initialization, the sensor remains in manual run mode even when no moti on activity is detected. the host can use the external powerdown or standby signals to achieve lower current consumption. ? standby pin (a) (active high): if set, the system goes into low power standby mode at the end of the current frame. typical power consumption in standby mode is shown in table 8 on page 19 . the internal clock and motion engine are switched off and so the VD5377 does not respond to any i 2 c communication and no motion activity is detected. all register settings are mainta ined in this state, so when standby is de- asserted the system immediately resumes in run mode. ? powerdown pin: if set, this signal immedi ately disables the internal 1.8 v core regulator. after power down, the system needs to be re-initialized. power consumption is typically <1 a in this state. figure 7. manual power mode flow diagram a. during initialization, the user must set the use_standby _pin register bit (system_config 0x05 bit 4) to 1 to enable the standby pin function otherwise it is ignored. mcu boot sw stby manual run mode automatic host_config_done = 1 automatic = 0 host_config_done = 1 automatic = 1 powerdown standby manual power mode standby=1 standby=0 powerdown=1 powerdown=0 powerdown=1 power up
doc id 022952 rev 2 19/88 VD5377 system overview table 8 summarizes the typical operating current in manual mode. figure 8 describes the power-up sequence of the VD5377. figure 8. manual power mode timing diagram after the mcu boot sequence is completed, the system enters sw stdby state and the motion pin is set to 1 indica ting that the device is ready to receive commands from the host. after initialization by the host over i 2 c, the device enters the manual run state and the motion pin goes low. note: the motion pin polarity is programmable. if active low polari ty is selected during initialization, the motion pin will remain high. if the standby pin is asserted, the system co mpletes the current frame operation before entering the standby state and stopping the in ternal system clock. when the standby pin is deasserted, the system clock is restar ted and the device resumes in the run state (no re-initialization required). if the powerdown pin is asserted (active high), the internal 1.8 v regulator is disabled and the 1.8 v core supply is switched off. when the table 8. typical power consumption (1) - manual mode 1. includes led (maximum exposure) run (2) 2. internal clock = 44 mhz; led_dac 14 ma; maximum exposure standby power down 3k3 kf/s 2 kf/s 1 kf/s 10.2 ma 6.9 ma 4.5 ma 25 a <1 a vtop dvdd/avdd por system clock powerdown (i) system states power up sw stdby manual standby powerdown power up standby (i) motion (o) i2c (i/o) mcu boot running state state manual running host_config_done power up mcu boot standby pin latency up to 1 frame duration t1 t2 t3 t5 t2 device ready t4
system overview VD5377 20/88 doc id 022952 rev 2 powerdown pin is deasserted, the internal 1.8 v regulator is re-enabled triggering a por (power-on reset) and the mcu re-initializes as at power-up before entering the sw stby state. the device must be re-configured after powerdown. key timing parameters are shown in table 9 . table 9. manual mode timing constraints symbol parameter typical t1 por delay (por threshold = 1.4 v typ) 20 s t2 clock startup 1 s t3 mcu boot time 450 s t4 minimum powerdown time (220 nf regulator capacitor) 10 ms t5 (1) 1. no i 2 c comms permitted to VD5377 after standby pin asserted standby pin latency (up to 1 frame at 1 kf/s) up to 1 ms
doc id 022952 rev 2 21/88 VD5377 system overview 4.2 automatic power management automatic power mode is the advanced powe r saving mode of the VD5377. when this mode is activated, th e sensor automatically enters low power modes (ca lled sleep states) after a given time if the sensor does not detect any motion. figure 9. automatic power mode flow diagram a sleep state is a low power state where the in ternal system cl ock is disabled, the analog block is powered down and only the internal 50 khz oscillator is running to wake the sensor up periodically. each time the sensor wakes up, a single frame is captured and the motion versus previous frame is estimated. if motion is detected the system resumes in run mode; otherwise if no motion is detected the sens or goes back to sleep . up to three sleep states (default) can be selected. the sleep time-out and wake-up latency periods are programmable. boot sw stby manual run mode automatic host_config_done = 1 automatic = 0 host_config_done = 1 automatic = 1 powerdown automatic power mode sleep 1 sleep 2 sleep 3 powerdown=0 powerdown=1 powerdown=1 50 ms 8 secs 10mins 10 ms 100 ms 500 ms default sleep time-outs and wakeup latencies are shown. these parameters are power up programmable.
system overview VD5377 22/88 doc id 022952 rev 2 in automatic power mode, if the use_standby_ pin register is set, the standby pin is configured as a chip select (active low) to perform i 2 c communications. this allows the host to perform i 2 c communications to the VD5377 at any time even during sleep modes. if the use_standby_pin register is not se t, the host can only perform i 2 c communications when motion data is pending. low power states: ? sleep states: typical power co nsumption in the various sl eep states is shown in table 10 . ? powerdown pin: if set, this signal immedi ately disables the internal 1.8 v core regulator. after power down, the system needs to be re-initialized. power consumption is typically <1 a in this state. figure 10 describes the power-up sequence of the VD5377 in automatic power management mode. after the mcu boot sequenc e is completed, the system enters sw stdby state and the motion pin is set to 1 in dicating that the device is ready to receive commands from the host. after initialization by the host over i 2 c, the device enters the auto run state and the motion pin will go low. note: the motion pin polarity is programmable. if active low polari ty is selected during initialization, the motion pin will remain high. after a time, motion is detected and the motion pin goes high. once motion is detected the device can no longer enter sleep until all pending motion data has been read. the host deasserts the standby pin to enable i 2 c comms (if use_standby_pin register was set in initialization routine); motion data is read and the standby pin is re-asserted. after the runningtimeout period, if no further motion is detected, the device enters the sleep1 state. after the sleep1latency period, the de vice wakes up for 1 frame to detect any movement. no motion is detected so the device remains in the sleep1 state. if the powerdown pin is asserted, the internal 1.8 v regulator is disabled and the 1.8 v core supply is switched off. when the powerdo wn pin is deasserted, the internal 1.8 v regulator is re-enabled and the mcu re-initializes as at power-up before entering the sw stby state. the device must be re-configured after powerdown. table 10. typical power consumption (1) - automatic mode 1. includes led (maximum exposure) run (2) 2. internal clock = 44 mhz; led_dac 14 ma; maximum exposure sleep1 sleep2 sleep3 power down 3.3 kf/s 2 kf/s 1 kf/s 10.2 ma 6.9 ma 4.5 ma 350 a 60 a 20 a <1 a
doc id 022952 rev 2 23/88 VD5377 system overview figure 10. automatic power mode timing diagram (use_standby_pin=1) key timing parameters are shown in table 11 . vtop dvdd/avdd por osc 48 mhz powerdown (i) system states power up sw stdby auto sleep1 powerdown power up standby (i) motion (o) i2c (i/o) mcu boot running state state host_config_done power up mcu boot device ready osc 50 khz runningtimeout sleep1latency 1 frame wake-up duration motion read motion detected through i2c with standby as chip select t1 t3 t2 t4 table 11. automatic mode timing constraints symbol parameter typical t1 por delay (por threshold = 1.4 v typ) 20 s t2 clock startup 1 s t3 mcu boot time 450 s t4 minimum powerdown time 10 ms
i/o description VD5377 24/88 doc id 022952 rev 2 5 i/o description 5.1 i2c_sel[2:0] the default i 2 c address is 0xa6. however, in some applications the default address may conflict with other i 2 c devices sharing the bus or it may be necessary to chain multiple ofn devices on the same bus. for that reason, the user can select from one of seven i 2 c addresses as shown in table 12 . the i2c_sel pads have internal pull-down re sistors and can be left unconnected for the default address. for any other address, connect pads that require a logic ?1? to dvdd (the internal pull-down resistor is automatically disconnected afte r the internal microcontroller boot sequence is completed to conserve power). if required, custom configurations can be stor ed in rom on the device corresponding to a particular i 2 c address to reduce the number of required register writes by the host. if interested in this feature, pl ease contact stmicroelectronics. the device i 2 c address can also be configured dyna mically by writing to register devaddr (0x7c) bits [7:1] (see table 13 ). this sets the 7-bit base i 2 c address of the device and allows multiple devices with the same default address to be re-mapped dynamically. this operation must be done in 2 steps: ? program register 0x7c using the curren t device address to program the new one ? access registers with the new device address each device must be powered in turn to reconfigure its address and this operation must be repeated each time t he system is initialized. table 12. user-selectable i 2 c addresses i2csel[2:0] 8-bit i 2 c address 000 0xa6 001 reserved 010 0xc6 011 0xd6 100 0xe6 101 0x36 110 0x46 111 0x20 table 13. control register to dynamically configure device i 2 c address addr (hex) register name signal name bit type default (hex) comment 7c devaddr i2cs_index_auto_inc_en 0 prw 01 auto increment function i2cs_dev_addr 7:1 prw 53 i 2 c device address
doc id 022952 rev 2 25/88 VD5377 i/o description 5.2 led_out (tracking led) and gpio0 led_out is controlled by a 3-bit current dac (0x3 analog_ctrl2 bits [6:4]) capable of driving up to 14 ma (current sink). where higher power output is required, an external led driver can be used controlled by gpio0 (0x3 analog_ctrl2 bit7 and 0xd gpio_gpio0 bit 4). figure 11 shows the two led drive options. led pulse timing is controlled automatically (see figure 12 ). gpio0 can also be used as a general purpose i/o and is configured using register 0xd gpio_gpio0 bit 4. a typical configuration of a gpio is shown in figure 13 on page 27 . figure 11. led drive options figure 12. led control led_out led driven by internal dac vtop VD5377 gpio0 led with external driver vtop VD5377 led led short exposure long exposure 1 frame = 1ms (1khz) / 500s (2khz) / 250s (4khz) 86 s (max)
i/o description VD5377 26/88 doc id 022952 rev 2 table 14. control register for led_out and gpio0 addr (hex) register name signal name bit type default (hex) comment 3 analog_ctrl2 led_dac_control 6:4 prw 07 adjust led drive dac drive output current. 0 = iout = 0 ma 1 = iout = 2.0 ma 2 = iout = 4.0 ma 3 = iout = 6.0 ma 4 = iout = 8.0 ma 5 = iout = 10.0 ma 6 = iout = 12.0 ma 7 = iout = 14.0 ma (default) led_out_polarity 7 prw 01 led_out_en polarity 0 = high when led must be on 1 = low when led must be on d gpio_gpio0 gpio_gpio0_en 0 prw 00 gpio0 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_gpio0_a 1 prw 00 gpio0 data output (when _en = 0) gpio_gpio0_zi 2 pr 00 gpio0 io value gpio_gpio0_a_ctrl 4 prw 00 gpio0 data output select, either as led_out_en or from register bank. 0 = output value from hw register 1 = led_out_en (polarity set in register 0x3 analog_ctrl2 bit 7) gpio_gpio0_opendrain 7 prw 00 gpio0 pad open drain control 0 = gpio0 pad normal config 1 = gpio0 pad in open drain (a=en)
doc id 022952 rev 2 27/88 VD5377 i/o description figure 13. typical configuration of gpio table 15. truth-table gpio_opendrain gpio_en gpio_a or led_ctrl condition output 000output0 001output1 0 1 x input - 1 x 0 open-drain 0 1 x 1 open-drain tri-state en a zi io gpio_en gpio_a gpio_a_ctrl gpio_opendrain 0 1 digital logic led_ctrl 0 1 register bank io pad input
i/o description VD5377 28/88 doc id 022952 rev 2 5.3 motion the motion pad is a 3.0 v digital i/o pad re ferenced to vtop and can be configured either as a push/pull output or open-drain. it combines the functions of motion pending flag and power-on reset indicator (see figure 14 ). the motion signal is driven low at power-up and stays low until the internal mcu boot s equence is completed. once the boot sequence is completed the motion signal goes high and remains high until the device is configured and enters the automatic or manual run st ate. thereafter the level on the motion pad depends on the motion pin polarity se tting (register 0x5 system_confi g bit 2). note: in powerdown, a 35 kohm pull-down resistor is activated in the motion pad. this may result in leakage current in the external circuit. also, in open-drain configurat ion, careful choice of pull-up resistor is required to ensure the resultant intermediate voltage on the motion pad does not induce leakage current in the motion input gate. figure 14. motion behavior at power-up por motion state power up sw stdby auto run or manual run mcu boot table 16. control register for motion pin polarity addr (hex) register name signal name bit type default (hex) comment 5 system_config automatic_power_mode 0 prw 01 power mode scheme 0 = manual 1 = automatic motion_pin_polarity 2 prw 00 motion pin polarity (in non idle system state) 0 = motion pin low when motion detected 1 = motion pin high when motion detected host_config_done 3 prw 00 bit needs to be set by host when configured after power up. use_standby_pin 4 prw 01 standby pin is used as chip select to enable i 2 c in auto power mode and standby pin is used to wake up the osc/dvreg (in sleep states in auto power mode). 0 = standby pin not used 1 = standby pin is used system_state 7:5 rw 01 legacy register - please use system_state (0x91) instead.
doc id 022952 rev 2 29/88 VD5377 i/o description 5.4 standby the standby pad is a 1.8 v digital input (a ctive high/ 5 v tolerant). in manual run mode, if standby is asserted the devi ce enters a low power standby state at the end of the current frame (see figure 7: manual power mode flow diagram on page 18 ). when standby is de-asserted the device resumes in run mode without requiring re- initialization. in automatic run mode, the standby pin acts as a i 2 c enable (see figure 15 ). when standby = 0, i 2 c is enabled and the VD5377 will respond to i 2 c communication from the host in either run or any of the sleep states. when standb y = 1 the VD5377 consumes less power but will not respond to i 2 c communication. in order to use the standby pin in automatic mode the use_sta ndby_pin (register 0x5 system_config bit 4 in table 17: features and scaling on page 32 ) must be set during system initia lization. if this function is not required, the use_standby_pin register should be set to 0 and the standby pad should be connected to either vdd or vss. note: if use_standby_pin = 1, the standby pin must be set to 0 before each i 2 c transaction even if motion data is pending. c gpio_motion gpio_motion_en 0 prw 00 motion output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_motion_a 1 prw 01 motion data output (when _en = 0) gpio_motion_zi 2 pr 01 motion io value gpio_motion_pd 3 prw 01 motion pull-down control (internal 35 kohms pull-down resistor) - active low 0 = io is pulled down 1 = io not pulled down gpio_motion_a_ctrl 4 prw 00 motion data output origin 0 = output value from hw register 1 = output value from motion detect ip reserved 6:5 prw 02 reserved gpio_motion_opendrain 7 prw 00 motion pad open drain control 0 = motion pad normal config 1 = motion pad in open drain (a = en) table 16. control register for motion pin polarity (continued) addr (hex) register name signal name bit type default (hex) comment
i/o description VD5377 30/88 doc id 022952 rev 2 figure 15. in automatic mode the standby pin functions as i 2 c enable if use_standby_pin is selected 5.5 powerdown powerdown is a 3.0 v capable analog input pa d referenced to vtop. the input switching level is 0.8 v and is compat ible with 1.8 v and 2.8 v systems. when powerdown is set to 1 the core 1.8 v digital supply is switched of f. the device typically consumes <1 a in this state (a) . when powerdown is set to 0, the intern al 1.8 v core regulator is enabled and the power-up sequence is initiated (see figure 8: manual power mode timing diagram on page 19 ). the device requires full re -initialization after powerdown. note: in a 1.8 v direct drive configuration w here the internal regulator is not used, the powerdown pin should be connected to vdd to ensure the regulator is disabled (see figure 4: 1.8 v direct supply on page 14 ). motion internal osc state sleep run run standby i 2 c comms minimum time = 10 us a. see the note in section 5.3: motion on page 28 .
doc id 022952 rev 2 31/88 VD5377 key features 6 key features this chapter gives an overview of some of the most important registers and functions. 6.1 feature count feature count is a measure of the useful detail in an image which is used to match successive frames. generally, the higher the feature count the better the tracking. the features register (0x31) in figure 17 is an 8-bit value representing the 8 msbs of a 12-bit internal register. a maximum value of 255 represents a feature count of 16 x 255 = 4080. a reasonable average target feature count is around 2000. feature counts averaging less than 1000 are likely to result in missing counts and sluggish navigation. this is usually as a result of low contrast in the image or significant vignetting due to the lens. note: on some textured surfaces the feature count may exceed 4080. when this occurs the features register clips at 255. this is normal and does not affect tracking. 6.2 minimum features threshold without any object on the sens or the feature coun t will be non-zero, typically around 200. this residual value is usually due to the char acteristics of the lens and/or pixel noise but may also be caused by internal or external light reflection which can sometimes result in unintentional cursor movement (or jitter). to prevent this unwanted movement, the motion engine is inhibited until the feature count re gister exceeds the value in the min_features register (0x29). multiply the register value by 16 to get the actual feature count threshold. default value is 16d x 16 = 256. 6.3 x/y scaling the VD5377 outputs a single count for each one pixel displacement of the object. the physical dimension of one pixel is 30 m . the actual displacement depends on the magnification of the lens used. for a lens of magnification m = 0.5 one pixel displacement equates to 60 m physical displacement of the object. cursor movement is typically expressed in coun ts or dots per inch (cpi or dpi). in this case (m = 0.5): counts per inch = 25.4mm/60m = 423 cpi the x/y scaling registers ( table 17: features and scaling on page 32 ) can be used to increase or decrease the native cpi according to the following equation: counts per inch = register_value x m x 100 scale factors can be applied to x and y independently to compensate for any lens distortion.
key features VD5377 32/88 doc id 022952 rev 2 table 17. features and scaling addr (hex) register name signal name bit type default (hex) comment 29 min_features min_features 7:0 prw 10 this register represents the minimum feature count below which motion is inhibited. multiply by 16 to get the actual feature count threshold. default is 16d x 16 = 256. 2a x_scaling motion_x_scaling 7:0 prw 10 scaling for x motion vectors. resolution is calculated as register value x 100 x m, where m is the lens magnification. so, for m = 0.5: 0x08 = 400 cpi that is 8 x 100 x 0.5 0x0c = 600 cpi that is 12 x 100 x 0.5 2b y_scaling motion_y_scaling 7:0 prw 10 scaling for y motion vectors. resolution is calculated as register value x 100 x m, where m is the lens magnification. so, for m = 0.5: 0x08 = 400 cpi that is 8 x 100 x 0.5 0x0c = 600 cpi that is 12 x 100 x 0.5 31 features features_report 7:0 pr 00 feature count report, as the sum of absolute differences between pixels and the field average. bits [11:4] are represented here so x16 to calculate the actual feature count. maximum value is 4080 = 255 x 16.
doc id 022952 rev 2 33/88 VD5377 key features 6.4 automatic exposure control figure 16 describes the automatic exposure control function. this routine is performed every expo_frame_update (regis ter 0x4b).the auto-exposure control algorithm works by adjusting exposure until the brightest (max exposed (a) ) pixel in the frame lies within a specified target range. this is to ensure that no part of the frame is saturated. figure 16. automatic exposure algorithm manual or automatic exposure control can be selected. this is cont rolled using register exposure_control 0x43 bit 0 (see table 18 ). bits [6:4] give the exposure status and bit 7 is the exposure limit flag. in automati c exposure control m ode, register expotime a. in fact the second brightest pixel is used. note that aec operates on the exposed frame, that is, before noise cancellation. processing is done on the cds frame wh ich is derived from the exposed frame as follows: cds frame = exposed frame - black frame + 8 mep = 255? expo = min(0, expo - satdecstep ) status = saturated mep > mep_hight expo = min(0, expo - decstep ) status = high (overexposed) mep < mep_lowt expo = max(255, expo + incstep ) status = low (underexposed) status = stable expo > expomax expo = expomax limitflag = 1 expo < expomin expo = expomin end programmable parameters shown in red start no no no yes ye s yes no no yes yes
key features VD5377 34/88 doc id 022952 rev 2 0x47 gives the current exposure time. this register is also used to enter the required exposure time in manual exposure mode. register 0x44 is the max_expo_pix (read- only). registers 0x45/0x46 are the upper and lower exposure targets (180 to 240 by default). when the mep is within this range the exposure is judged to have ?converged? and no further exposure updates are required until the m ep moves outside the target range. it is not normally required to adjust the exposure targets. the default exposure range is 1 to 255. these limits are programmable with registers 0x49/0x4a. by default, exposure update rate is every tw o frames. this can be adjusted using register 0x4b. exposure convergence can be modified by changing the exposure increment/decrement step sizes with registers 0x4e/0x4f/0x50. table 18. exposure control addr (hex) register name signal name bit type default (hex) comment 43 exposure_control autoexpo_en 0 rw 01 auto exposure control 0 = disable 1 = enable autoexpo_status 6:4 r 00 auto exposure status 0 = undef (no aec performed yet) 1 = low (exposure increasing) 2 = stable (max exposed pixel within range) 3 = high (exposure decreasing) 4 = saturated (exposure saturation decreasing) autoexpo_limit_flag 7 r 00 exposure limit reached flag 0 = exposure time within range 1 = exposure time limit reached 44 max_expo_pix max_exposed_pixel_v alue 7:0 pr 00 second maximum pixel value of the current frame (before cds) 45 max_expo_pix_thre sh_high max_exposed_pixel_t hresh_high 7:0 rw f0 high threshold value of max exposed pixel where the aec is stable. 46 max_expo_pix_thre sh_low max_exposed_pixel_t hresh_low 7:0 rw b4 low threshold value of max exposed pixel where the aec is stable. 47 expotime exposure_time 7:0 prw 40 exposure time value in 3 mhz clk period step (333ns)
doc id 022952 rev 2 35/88 VD5377 key features 6.5 5 x 5 high pass filter before each frame is processed the image data is passed through a high-pass filter to extract edge information. the para meters_3 register 0x28 bit 5 ( table 19 ) permits selection between two high pass filter opti ons. 3 x 3 is the default high-pass filter. the alternative 5 x 5 high-pass filter has a lower cut-off frequency and so preserves more information in lower contrast images. this may help improve tracking performance in some situations, although a possible effect is an increase in hover (this can be overcome by increasing min_features th reshold, register 0x29). 49 expotime_max exposure_time_max 7:0 rw ff maximum exposure time applied by the aec. 4a expotime_min exposure_time_min 7:0 rw 01 minimum exposure time applied by the aec. 4b expo_frame_updat e autoexpo_frame_upda te 7:0 rw 01 exposure update frequency (every n+1 frames). default is every two frames. 4e expotime_inc_step ex po_inc_step 7:0 rw 04 exposure increment step (used when below max_expo_pix_thresh_low). 4f expotime_dec_step expo_dec_step 7:0 rw 04 exposure decrement step (used when above max_expo_pix_thresh_high). 50 expotime_sat_dec_ step expo_sat_dec_step 7:0 rw 10 exposure decrement step (used when above max_expo_pix is saturated = 255). table 18. exposure control (continued) addr (hex) register name signal name bit type default (hex) comment table 19. 5x5 high-pass filter register addr (hex) register name signal name bit type default (hex) comment 28 parameters_3 reserved 3:0 prw 04 reserved reserved 4 prw 01 reserved hpf_5x5_sel 5 prw 00 select between 3 x 3 and 5 x 5 high pass filter. 0 = 3 x 3 high pass filter 1 = 5 x 5 high pass filter reserved 6 prw 01 reserved
key features VD5377 36/88 doc id 022952 rev 2 6.6 sunlight timing in applications where strong external ambient lighting could interfere with tracking such as direct sunlight, ? sunlight dmib timing ? mode is recommended (0x51 bit 1 = 1). this can either be set to always on, that is 0x51 = 0x2 or set to change automatically when the sensor detects high ambient light co nditions (that is, 0x51 = 0x1). see table 20 . the default is ?normal dmib timing? mode. note: the maximum permitted frame rate in sunlight timing mode is 3.3 kf/s (see section 6.7: automatic/manual frame rate ). table 20. sunlight dmib timing mode addr (hex) register name signal name bit type default (hex) comment 51 control dmib_ctrl_mode 0 rw 00 dmib controller timing switch mode 0 = manual (chosen by dmib_timing register) 1 = automatic (system auto sets the dmib_timing mode, status reported in dmib_timing register) dmib_timing 1 prw 00 dmib controller timing mode 0 = normal dmib timing (same as 376 with double expo time possible) 1 = sunlight dmib timing reserved 7 prw 00 reserved
doc id 022952 rev 2 37/88 VD5377 key features 6.7 automatic/manual frame rate the VD5377 can operate in either automatic or manual frame rate control mode. the default frame rate control mode is automatic ( see table 21 , register 0x1c bit 4). this means that the device adjusts frame rate automatically dependin g on the tracking velocity. by default, frame rate is adjusted in the range 1 k to 2 k to max. because power consumption increases as frame rate increase s, automatic frame rate control is th e most efficient in terms of power consumption and requires no additional over head from the host cpu. the maximum frame rate to be applied in auto frame rate mode is set with register 0x1c bits 7:5. the default maximum frame rate is 3.3 kf/s. manual frame rate is selected with register 0x1c bits [2:0]. due to cpu bandwidth limitations of the on-boa rd mcu, maximum frame rate is limited to 3.3 kf/s in sunlight timing mode. in normal dmib timing mode only (default mode - register 0x51 = 0), the maximum frame rate may be increased up to 4 kf/s but in order to meet internal timing constraints, the maximum exposure time (expotime_max 0x49) needs to be reduced according to table 22 . the motion_threshold_low_comp (spare 0x32) should also be updated. table 21. adaptive frame rate control addr (hex) register name signal name bit type default (hex) comment 1c frame_rate_cont rol frame_rate_sel 2:0 prw 02 frame rate selection (value for internal osc running @48 mhz) 0 = 0.5kf/s (2 ms period) 1 = 1 kf/s (1 ms period) 2 = 2 kf/s (500 us period) 3 = 2.5kf/s (400 us period) 4 = 2.9kf/s (350 us period) 5 = 3.3kf/s (300 us period) 6 = 3.6kf/s (275 us period) 7 = 4 kf/s (250 us period) frame_rate_ctrl 4 rw 00 frame rate management control 0 = automatic (1 k / 2 k / max f/s auto frame rate) 1 = manual (set with frame_rate_sel reg) max_auto_frame_r ate 7:5 rw 05 maximum frame rate to be applied in auto frame rate mode. 0 = not allowed 1 = not allowed 2 = 2 kf/s (500 us period) 3 = 2.5 kf/s (400 us period) 4 = 2.9 kf/s (350 us period) 5 = 3.3 kf/s (300 us period) 6 = 3.6 kf/s (275 us period) 7 = 4 kf/s (250 us period)
key features VD5377 38/88 doc id 022952 rev 2 table 22. modified exposure limits frame rate control mode automatic manual maximum frame rate 3.3 kf/s 3.6 k f/s 4 kf/s 3.3 kf/s 3.6 kf/s 4 kf/s maximum exposure 255 232 157 255 249 174 table 23. motion threshold addr (hex) register name signal name bit type default (hex) comment 32 spare reserved 0 rw 00 reserved reserved 1 rw 00 reserved motion_threshold_l ow_comp 7:4 rw 03 update motion_threshold_low register for adaptive frame rate: 0 = 4 kf/s 2 = 3.6 kf/s 3 = 3.3 kf/s
doc id 022952 rev 2 39/88 VD5377 additional features 7 additional features 7.1 auto-movement filter an auto-movement filter has been added in VD5377 rev 2.0 to enhance the navigation performance in high ambient light conditions. the filter can only be enabled in automatic power mode (b) . on initial wakeup, after sleep, the filter will hold the sensor in the lowest run stat e until motion is seen is x times in y period. both x and y are programmable. with the default settings, the amf will look for mo tion in three separate 7 ms periods. once motion is seen in one 7 ms perio d, the filter will immediatel y move onto the next 7 ms period. b. automatic power mode without standby (system_config 0x5 = 0x09) does not functi on correctly when the auto-movement filter is enabled. suggested workaround is to use automatic power mode with use_standby_pin enabled. alternatively, there is a firmware patch avai lable which can be request ed from stmicroelectronics. table 24. auto-movement filter addr (hex) register name signal name bit type default (hex) comment 8d auto_movement_ ctrl1 bautomovefilteren able 0rw00 auto movement filter enable 0 = disable 1 = enable ucautomovefilterfr amenb 6:1 rw 07 number of frames on which the auto movement filter is applied (must be greater than 1). bautomovesaturate dexpo 7rw00 when image in high light and exposure (reg 0x47) is set to 1, flag used by engine to discard motion in this condition. 0 = disable 1 = enable
additional features VD5377 40/88 doc id 022952 rev 2 8e auto_movement_ ctrl2 ucautomovefilterl atency 3:0 rw 01 latency between frames on which the auto movement filter is applied. 0 = 400 us 1 = 1 ms 2 = 1.4 ms 3 = 2 ms 4 = 4 ms 5 = 10 ms 6 = 20 ms 7 = 50 ms 8 = 100 ms 9 = 150 ms 10 = 200 ms 11 = 500 ms 12 = 1 s 13 = 1.5 s 14 = 2 s 15 = 2.6 s ucautomovefilterl oop 7:4 rw 03 set the number of sequences to detect motion to grant motion in sleep mode. table 24. auto-movement filter (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 41/88 VD5377 additional features 7.2 adaptive cpi to be able to cope with la rge screen resolution an adaptive cpi functionality has been implemented in VD5377, where the motion sca ling can be adjusted depending on the speed of the detected motion. the algorithm is shown in figure 17 where maximum motion is max_abs_motion (register 0x2f). figure 17. adaptive cpi algorithm motion scaling (cpi) max_motion adaptcpi_min_motion adaptcpi_min_scaling reg 0x36 reg 0x35 adaptcpi_log_motion_range reg 0x37 [2:0] adaptcpi_log_scaling_range reg 0x37 [6:4] blue: adaptive cpi register control legend purple: default values 16 48 2 5 =32 8 24 2 4 =16 (1 pixel/32) table 25. adaptive cpi addr (hex) register name signal name bit type default (hex) comment 23 overflow adapt_cpi_en 6 prw 00 if set, the cpi is function of the detected motion. 0 = no adaptive cpi 1 = enable adaptive cpi 2f max_abs_motion max_abs_motion 6:0 pr 00 max(abs(x motion), abs(y motion)) either from integrated or instant motion 35 adaptcpi_min_ motion adaptcpi_min_ motion 7:0 prw 10 minimum value of max(|x frame motion|, |y frame motion|) from which the cpi is adaptive (if feature enabled) - multiply by 1/32 36 adaptcpi_min_ scaling adaptcpi_min_ scaling 7:0 prw 08 minimum motion scaling value when adaptive cpi feature is enabled.
additional features VD5377 42/88 doc id 022952 rev 2 7.3 backled[2:0] three pads are provided to optionally drive up to three backlight leds. each pad is a 4 ma (current limited), digital i/ o with open-drain capability whic h can drive up to three leds independently or can be combined to drive a single led up to 12 ma (see figure 18. ). each output can be controlled by an independent pw m controller to provide a versatile dimming function. when combined, all three pads are driven by pwm0. the pwm signals are automatically gated during pixel integration to ensure there is no light pollution of the tracking function. backled c ontrol registers are shown in table 26 . these pads can also be used as gpio. note: the backled[2:0] pads are tri-state by default and should be connected to ground if not used. 37 adaptcpi_ranges adaptcpi_log_ motion_range 2:0 prw 05 log value of motion range from which the cpi is adaptive (that is max motion = min + 2^adaptcpi_log_motion_range) 0 = motion range = 1 1 = motion range = 2 2 = motion range = 4 3 = motion range = 8 4 = motion range = 16 5 = motion range = 32 6 = motion range = 64 7 = motion range = 128 adaptcpi_log_ scaling_range 6:4 prw 04 log value of motion scaling range from which the cpi is adaptive (that is max scaling = min + 2^adaptcpi_log_scaling_range) 0 = scaling range = 1 1 = scaling range = 2 2 = scaling range = 4 3 = scaling range = 8 4 = scaling range = 16 5 = scaling range = 32 6 = scaling range = 64 7 = scaling range = 128 table 25. adaptive cpi (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 43/88 VD5377 additional features figure 18. backled configuration backled0 vtop backled1 backled2 VD5377 backled0 vtop backled1 backled2 VD5377 x3 backlight led scheme single backlight led scheme table 26. backled control registers addr (hex) register name signal name bit type default (hex) comment 9 gpio_backled0 gpio_backled0_en 0 prw 00 backled0 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_backled0_a 1 prw 01 backled0 data output (when _en = 0) gpio_backled0_zi 2 pr 01 backled0 io value gpio_backled0_tm 3 prw 00 reserved. do not modify this bit. gpio_backled0_a_ ctrl 4prw 00 backled0 data output origin 0 = output value from hw register 1 = output value from pwm 0 gpio_backled0_ opendrain 7prw 01 backled0 pad open drain control 0 = backled0 pad normal config 1 = backled0 pad in open drain (a=en)
additional features VD5377 44/88 doc id 022952 rev 2 a gpio_backled1 gpio_backled1_en 0 prw 00 backled1 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_backled1_a 1 prw 01 backled1 data output (when _en = 0) gpio_backled1_zi 2 pr 01 backled1 io value gpio_backled1_tm 3 prw 00 reserved. do not modify this bit. gpio_backled1_a_ ctrl 4prw 00 backled1 data output origin 0 = output value from hw register 1 = output value from pwm 1 gpio_backled1_ opendrain 7prw 01 backled1 pad open drain control 0 = backled1 pad normal config 1 = backled1 pad in open drain (a = en) b gpio_backled2 gpio_backled2_en 0 prw 00 backled2 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_backled2_a 1 prw 01 backled2 data output (when _en = 0) gpio_backled2_zi 2 pr 01 backled2 io value gpio_backled2_tm 3 prw 00 reserved. do not modify this bit. gpio_backled2_a_ ctrl 4prw 00 backled2 data output origin 0 = output value from hw register 1 = output value from pwm 2 gpio_backled2_ opendrain 7prw 01 backled2 pad open drain control 0 = backled2 pad normal config 1 = backled2 pad in open drain (a = en) f pwm_period pwm_period 7:0 prw ff pwm period duration (20 us tick period) 10 pwm_pulsehigh0 pwm_pulse_high0 7:0 prw 00 pwm 0 pulse high duration (20 us tick period) - 0 = disable 11 pwm_pulsehigh1 pwm_pulse_high1 7:0 prw 00 pwm 1 pulse high duration (20 us tick period) - 0 = disable 12 pwm_pulsehigh2 pwm_pulse_high2 7:0 prw 00 pwm 2 pulse high duration (20 us tick period) - 0 = disable table 26. backled control registers (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 45/88 VD5377 additional features 83 backlight_ control bbacklightenable 0 rw 00 backled pwm enable 0 = disable 1 = enable bsinglebackled 1 rw 00 single backled scheme control par pwm0 only 0 = 3 independent backleds 1 = backled controlled by pwm 0 bpwmpolarity 2 rw 00 backled pwm signal polarity 0 = high when led must be on (=pwm0) 1 = low when led must be on (=!pwm0) bbackledgaterena ble 3rw 00 enable the gating of backled pwm signal with dmib gater signal 0 = disable 1 = enable bpwmholdenable 4 rw 00 enable the hold mechanism when dmib gater signal is on 0 = disable 1 = enable bbacklightreset 7 rwc 00 in sw stby, rese t the control of backlight control (self cleared) 0 = disable 1 = enable table 26. backled control registers (continued) addr (hex) register name signal name bit type default (hex) comment
additional features VD5377 46/88 doc id 022952 rev 2 7.3.1 pwm operation the following list is a summary of pwm operation ( figure 19 ). ? the pwm block is clocked by the internal 50 khz oscillator which means in standby state in manual power mode and in sleep states in automatic power mode the backlight leds are still running. ? maximum led period is 5.12 ms (256 x osc50k clock period). ? programmable pulse width (from 0 to 5.12 ms). ? backled pulses can be ?gated? or ?delayed? during the tracking led ?on? time to avoid interference with the tracking function. this should not be required if the backled are shielded. note: no test is performed on pulsehigh value versus period value so the host must ensure that pulsehigh < period. figure 19. pwm operation: three independent pwm channels backled_en osc 50khz period period period pulsehigh1 pulsehigh0 pulsehigh2 pwm0 pwm1 pwm2
doc id 022952 rev 2 47/88 VD5377 basic start-up information 8 basic start-up information 8.1 register override to ensure correct operation over the device operating temperature range (see table 34: operating conditions on page 61 ) it is recommended to make the single register override specified in table 27 as part of the user initialization of the device in sw_standby. 8.2 recommended start-up settings the VD5377 needs to be initialized after power-up. the only required register write is host_config_done = 1 (system_con fig 0x5 bit 3). the rest of the start up settings vary depending on application type. the registers in table 28 are the most commonly used on power on. (see table 38: i2c register map on page 67 for more details about the registers.) table 27. analog_ctrl2 recommended setting addr (hex) register name default setting (hex) recommended setting description 3 analog_ctrl2 0xf4 0xfc bits [3:2] dmib dac vref setting = 1.6v table 28. start-up settings register address description 0x3 set led dac current (max is default) and register override 0xc set motion pin pin to open drain or push/pull (default) 0x27 set x/y direction 0x29 set min features (default = 256 [16 x 16d]) 0x2a / 0x2b set x/y scaling 0x51 set sun mode on (off is default) 0x5 (1) 1. customers are advised to set up the sensor (tha t is, cpi, xy direction and so on) before setting host_config_done. set auto/manual power mode, motion pin polarity, use_standby_pin and host_config_done
basic start-up information VD5377 48/88 doc id 022952 rev 2 as an example, the initialization ro utines could use the following sequence. 1. sensor in automatic power mode without ?use standby pin?, int led_dac set at max current, 800cpi (m = 0.5), motion pin polarity high (push-pull). ? register 0x5 = 0xd ([0] - automatic power mode, [2] - motion pin high, [3] - host config done) 2. sensor in automatic power mode with ?u se standby pin?, int led_dac set to 10 ma, register override, 800 cpi (m = 1), motion pin polarity high (open drain). ? register 0x3 = 0x5c ([3:2] - register override and [6:4] - led dac current) ? register 0xc = 0xce ([7:0] - motion open drain) ? register 0x2a/0x2b = 0x8 ([7:0] - 800 cpi for 1 x magnification) ? register 0x5 = 0x1d ([0] - automatic power mode, [2] - motion pi n high, [3] - host config done and [4] - use standby pin) 3. sensor in manual power mode with ?use standby pin?, int led_dac set at max current, 1000 cpi (m = 0.5), motion pin polarity low (push-pull), sunlight mode on, min features set to 1024. ? register 0x29 = 0x40 ([7:0] - min features) ? register 0x2a/0x2b = 0x14 ([7:0] - 1000 cpi for 0.5 x magnification) ? register 0x51 = 0x2 ([1:0] - sunlight mode on) ? register 0x5 = 0x18 ([0] - manual power mode, [2] - motion pin low, [3] - host config done and [4] - use standby pin)
doc id 022952 rev 2 49/88 VD5377 basic start-up information 8.3 reading x/y motion data the host can service motion data either by polli ng the motion signal on a regular basis or by using the motion signal to generate a host interrupt. the procedure for reading x/y motion vectors is shown in figure 20 . figure 20. reading x/y motion note: x/y motion registers 0x21 and 0x22 must be read consecutively using a multiple location i 2 c read sequence. see section 11.4.4: multiple location read on page 66 . x/y motion data is stored internally in a 17-bit accumulator ensuring that no data is lost even if the host cpu is delayed responding to motion. x/y motion data is read from the accumulator using register 0x21 and 0x22 (see table 29 ). 0x21/0x22 are 8-bit registers comprising 7 bits of data plus 1 sign bit. the x/y_overflow bits (register 0x23 bits 0 and 1) indicate when the x/y motion registers are full and there is more than 1 byte of data to be read. there is no overflow indica tor for the accumu lator but it is unlikely that an overflow will ever happen in practice. read x/y motion more motion? no exit yes motion detected? no (registers 0x21/0x22) yes
basic start-up information VD5377 50/88 doc id 022952 rev 2 table 29. x/y motion data addr (hex) register name signal name bit type default (hex) comment 21 x_motion x_motion 7:0 pr 00 x motion data since last polling was done. note that the internal accumulator is reduced from this value every time it is read. 22 y_motion y_motion 7:0 pr 00 y motion data since last polling was done. note that the internal accumulator is reduced from this value every time it is read. 23 overflow x_overflow 0 pr 00 this register records if the x- motion integrator has reached its limit. 0 = no overflow 1 = overflow y_overflow 1 pr 00 this register records if the y- motion integrator has reached its limit. 0 = no overflow 1 = overflow reserved 2 pr 00 reserved no_motion 3 pr 01 this bit is asserted as long as both x/y integrat ors are empty (logical or between motion_w and motion_y). 0 = motion 1 = no motion motion_acc_flush_ en 5prwc00 if set this bit flushes the motion accumulators (self cleared). adapt_cpi_en 6 rw 00 if set the cpi is function of the detected motion 0 = no adaptive cpi 1 = enable adaptive cpi reserved 7 prw 00 reserved
doc id 022952 rev 2 51/88 VD5377 basic start-up information 8.4 switching between autom atic mode and manual mode this section describes how to use low power standby mode in conjunction with automatic power management mode. low power standby has to be accessed from manual run as shown in figure 21 . manual run mode is accessed from automatic mode through sw stby. figure 21. accessing low power standby from automatic power mode the flowchart in figure 22 shows the procedure for going into low power standby mode from automatic power mode. note: automatic power mode with ?use standby pi n? must be used to enable switching between power management modes. sw stby manual run mode automatic host_config_done = 1 automatic = 0 host_config_done = 1 automatic = 1 standby standby=1 standby=0 host_config_done = 0
basic start-up information VD5377 52/88 doc id 022952 rev 2 figure 22. automatic mode to low power standby mode sensor in auto power mode with ?use standby pin? set. standby pin high - i 2 c unavailable set standby pin low (i 2 c enabled) read register 0x05 change bit 3 to 0 (host_config_done) write new value to register 0x05 read register 0x05 until sensor goes into software standby that is, register 0x05[7:5] = 0x01 write manual mode (bit[0] = 0) and host_config_done (bit[3] = 1) to register 0x05 set standby pin high standby set standby pin low read register 0x05 change bit 3 to 0 (host_config_done) write new value to register 0x05 read register 0x05 until sensor goes into software standby that is, register 0x05[7:5] = 0x01 write manual mode (bit[0] = 0) and host_config_done (bit[3] = 1) to register 0x05 set standby pin high sensor could be in any of the auto run/sleep modes set sensor in software standby mode wait until sensor goes into software standby mode set sensor in manual run mode manual standby mode (typical current = 15 ua) set sensor in software standby mode wait until sensor goes into software standby mode set sensor in manual run mode i 2 c disabled sensor in manual run mode
doc id 022952 rev 2 53/88 VD5377 basic start-up information 8.5 revision id the major and minor revision registers can be us ed to identify different revisions of the VD5377 silicon as shown in table 30 . currently, only two revisions exist: rev 1.0 (0.0) and rev 2.0 (1.0). register 0x90 is the device id and returns 0x4d (77 dec) when read. 8.6 soft reset in table 31 clearing register 0x16 bit 0 (software_reset_n) initiates an internal reset. all registers are initialized and th e mcu performs a reboot. this is equivalent to a power-on reset. table 30. major/minor revision registers addr (hex) register name signal name bit type default (hex) comment 0 major_revision majo r_revision 7:0 pr 01 major hardware revision number. updated in case of full mask regeneration. 0 = rev 1.x 1 = rev 2.x 2 = rev 3.x x = minor revision 1 minor_revision mino r_revision 7:0 rw 00 minor hardware revision number. updated in case of metal fix and or rom changes. 0 = rev 0 1 = rev 1 2 = rev 2 90 device_id ucdeviceid 7:0 rw 4d device id 0 = vd5376 (and previous) 77 = VD5377 table 31. soft reset addr (hex) register name signal name bit type default (hex) comment 16 resets software_reset_n 0 prwc 01 software reset re sult in full system reboot (active low - auto cleared) reserved 7:1 prw 0f do not modify these bits.
image capture VD5377 54/88 doc id 022952 rev 2 9 image capture 9.1 i 2 c image capture the chip can acquire a single frame coming from the image array (either cds, exposed or black frame), store it internally (in ram), and deliver its 400 pixels through i 2 c registers. a maximum of 105 frames per second can be achieved in this mode. the timing diagram ( figure 23 ) describes the sequence of steps carried out within a complete frame in i 2 c frame dump mode. figure 23. i 2 c frame dump timing diagram table 32 lists the registers related to the control of the i 2 c frame dump mode. framedump_en framedump_ready framedump_pixdata framedump_done black dmib out actual2 ram address cds out 0 1 2 3 398 399 pixel address exposed exposed - black actual2 ram r/w# 0 ... 399 0 1 2 3 398 399 1 i2c coms 2 3 t setup > 250us t frame > 9.4ms 1 : startup sequence of i2c frame dump mode 2 : i2c multiple read of 400 bytes 3 : exit sequence of i2c frame dump mode 0 0 : init sequence of i2c frame dump mode
doc id 022952 rev 2 55/88 VD5377 image capture table 32. i 2 c frame dump registers addr (hex) register name signal name bit type default (hex) comment 3 analog_ctrl2 led_out_dmib_ctrl 0 prw 00 select the source of led out. 0 = automatic (by dmib controller) 1 = direct ctrl (by led_out_manual) led_out_manual 1 prw 00 if led_out_dmib_ctrl is low, led driver enable control. 0 = led driver disable (direct ctrl) 1 = led driver enable (direct ctrl) dmib_dac_avdd_sel 3:2 prw 01 avdd select for dmib dac 0 = avdd1v5 = 1v45 1 = avdd1v5 = 1v5 2 = avdd1v5 = 1v55 3 = avdd1v5 = 1v6 led_dac_control 6:4 prw 07 adjust led drive dac drive output current. 0 = iout = 0 ma 1 = iout = 2 ma 2 = iout = 4 ma 3 = iout = 6 ma 4 = iout = 8 ma 5 = iout = 10 ma 6 = iout = 12 ma 7 = iout = 14 ma led_out_polarity 7 prw 01 led_out_en polarity 0 = high when led must be on (= dmib_led_on) 1 = low when led must be on (= !dmib_led_on) 15 clocks_lo clk_motion_timer 1 prw 00 timer clock enabled (forced always on). clk_framedump_en 5 prw 00 framedump clock enabled (forced always on). 16 resets framedump_reset_n 5 prw 00 framedump reset signal (active low) 19 control motion_engine_start 7 prw 00 timer interrupt enable. this enables the motion timer to operate. motion timer generates pulses that trigger frame capture and motion processing.
image capture VD5377 56/88 doc id 022952 rev 2 56 cdsout_sel cds_out_sel 1:0 prw 0 selects the output from the dmib controller (going to motion engine and or video output data). 0 = cds frame 2 = exposed frame 3 = black frame 58 framedump_ pixdata framedump_pixdata 7:0 pr 00 pixel data in frame dump mode. automatically increments to next pixel after a read of this register. 59 framedump_ctrl framedump_en 0 prw 00 frame dump mode enable 0 = disable 1 = enable framedump_start 1 pr 00 frame dump started framedump_ready 2 pr 00 flag set when a frame is ready to be read by host, pixel[0] is ready in register framedump_pixdata. framedump_done 3 pr 00 flag set when a complete frame (400 pixels) has been read. pci_test_enable 4 prw 00 muxed pci data onto pads (2 bits nibble + fst + qclk) 0 = disable 1 = enable framedump_mire 7 prw 00 in frame dump mode outputs a grey scale image (pixel_counter) 7c devaddr i2cs_index_auto_ inc_en 0 prw 01 auto increment function table 32. i 2 c frame dump registers (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 57/88 VD5377 image capture 9.1.1 step-by-step procedure the flow chart in figure 24 represents the implementation of the i 2 c frame dump mode from the host?s point of view. figure 24. flow chart procedure for i 2 c frame dump for i 2 c multiple read see section 11.4.4: mu ltiple location read on page 66 . framedump enable frame dump 1 - set clocks (write 0x15 = 0x22) 3 - set framedump_reset_n (set bit 5 of reg 0x16) 4 - select output image type - exp/black/cds (set 1:0 of reg 0x56) 5 - disable i 2 c auto increment (reset bit 0 of reg 0x7c) wait t setup i2c multiple read disable frame dump exit sequence of 400 bytes 5 - clear motion_engine_start ( reset bit 7 in register 0x19 ) 7 - wait for 250 us or poll bit 2 of register 0x59 8 - read 400 pixel data stored in register 0x58 9 - disable frame dump mode ( write 0x00 in register 0x59 ) 13 - reset clocks ( set register 0x15 to 0x00) 12 - clear framedump_reset_n (reset bit 5 of reg 0x16) 11 - re-enable i 2 c auto increment (set bit 0 of reg 0x7c) t frame * * : - a multiple read of 400 bytes correspond to the i 2 c sequence: start+device_addr(w)+index(0x58) +repeated_start+device_addr(r)+pi xel0+pixel1+...+pixel399+stop - if -due to some host limitation- such a long mult iple read is not possible , a similar sequence as below should be performed. example for a li mitation of 128 byte multiple read: start+device_addr(w)+ index(0x58)+repeated_start+device_ addr(r)+pixel0+...+pixel127+stop start+device_addr(w)+index(0x 58)+repeated_start+device_addr(r )+pixel128+...+pixel255+stop start+device_addr(w)+index(0x 58)+repeated_start+device_addr(r )+pixel256+...+pixel383+stop start+device_addr(w)+index(0x 58)+repeated_start+device_addr(r )+pixel384+...+pixel399+stop 10 - set motion_engine_start ( set bit 7 in register 0x19 ) 6 - enable frame dump mode ( write 0x01 in register 0x59) init sequence
image capture VD5377 58/88 doc id 022952 rev 2 9.1.2 debug mode the VD5377 implements a debug mode where a grey scale image can be output instead of the image data. to enter this mode, bit 7 of register 0x59 (?framedump_mire?) must be set. the output frame should resemble the picture in figure 25 . figure 25. i 2 c frame dump output in debug mode 9.2 fast capture to enter this test mode: 1. set register 0x5 = 0x18 - sensor in manual power mode and host_config_done set. 2. set bit 4 of registry 0x15 to 1 (clk_pci_en). 3. set bit 4 of registry 0x59 to 1 (pci_test_enable).
doc id 022952 rev 2 59/88 VD5377 image capture in this mode, the pins bk0, bk1, bk2 and i2c_sel0 are used for serial output of video data in the form of 2 bits nibble + fst and qclk. upon receipt of an fst (bk2) rising edge , nib_even (bk0) and ni b_odd (bk1) output data every 48 mhz clock cycle. the signals should be sampled the first rising clk (i2c_sel0) edge after the fst rising edge, and then every rising clk edge after that during the 1600 cycles (400 x 4). groups of four consecutive nib_even and ni b_odd must then be repackaged together to form a single 8-bit pixel data. this format enables the pixels to be output at the same frame rate as normal operation, and keeps i 2 c available to access the usual register settings. table 33. fast capture addr (hex) register name signal name bit type default (hex) comment 5 system_config automatic_power_ mode 0prw 01 power mode scheme 0 = manual 1 = automatic motion_pin_polarity 2 prw 00 motion pin polarity (in non idle system state) 0 = motion pin low when motion detected 1 = motion pin high when motion detected host_config_done 3 prw 00 bit needs to be set by host when configured after power up. use_standby_pin 4 prw 01 standby pin is used as chip select to enable i 2 c in auto power mode and standby pin is used to wake up the osc/dvreg (in sleep states in auto power mode). 0 = standby pin not used 1 = standby pin is used system_state 7:5 rw 01 legacy register - please use system_state (0x91) instead. 15 clocks_lo clk_motion_timer 1 prw 00 timer clock enabled (forced always on) clk_pci_en 4 prw 00 pci clock enable (forced always on) 59 framedump_ctrl pci_test_enable 4 prw 00 muxed pci data onto pads (2 bits nibble + fst + qclk) 0 = disable 1 = enable
image capture VD5377 60/88 doc id 022952 rev 2 figure 26. fast capture timing diagram bk2 (fst) bk0 (nib_even) bk1 (nib_odd) i2c_sel0 (48mhz qclk) 6 7 4 5 2 3 0 1 pixel_0[7:0] reconstructed pixel data pixel_1[7:0] pixel_399[7:0]
doc id 022952 rev 2 61/88 VD5377 electrical characteristics 10 electrical characteristics typical values are quoted for nominal voltage, process and temperature. maximum values are quoted for worst case conditions (process, voltage and functional temperature) unless otherwise specified. current measurements include led at maximum exposure. 10.1 operating conditions table 34. operating conditions symbol parameter minimum typical maximum unit supply voltage vtop external supply (using internal regulator) 2.2 - 3.0 v dvreg internal 1.8 v regulator tbd 1.8 tbd v dvdd external 1.8 v supply (direct drive configuration) 1.7 1.8 1.9 v internal system clock frequency fosc center frequency = 48 mhz center frequency = 44 mhz center frequency = 39 mhz center frequency = 34 mhz tbd 45.5 41.5 37.0 32.5 tbd mhz operating current (automatic mode) i vtop auto run (3.3 kf/s) - 10.2 tbd ma i vtop auto run (1 kf/s) - 4.5 tbd ma i vtop sleep 1 - 350 tbd a i vtop sleep 2 - 60 tbd a i vtop sleep 3 - 20 tbd a i vtop powerdown - 1 tbd a operating current (manual mode) i vtop manual run (3.3 kf/s) - 10.2 tbd ma i vtop manual run (1 kf/s) - 4.5 tbd ma i vtop standby - 25 tbd a i vtop powerdown - 1 tbd a led drive current led_out internal led driver: led_dac_setting = 7 (max) led_dac_setting = 4 (mid)) led_dac_setting = 1 (min) 14.0 8.0 2.0 tbd tbd tbd ma
electrical characteristics VD5377 62/88 doc id 022952 rev 2 10.2 digital i/o note: in table 35 , vdd = 1.8 v for all digital i/o except for motion, gpio0 and powerdown which are referenced to vtop. note: powerdown input s witching level is 0.8 v. 10.3 i 2 c timing storage and normal operating temperature t as storage temperature -40 - +85 c t an normal operating temperature -20 - +70 c table 34. operating conditions (continued) symbol parameter minimum typical maximum unit table 35. digital io electrical characteristics symbol parameter minimum typical maximum unit cmos digital inputs v il low level input voltage 0 0.3 vdd v v ih high level input voltage 0.7 vdd vdd v i il low level input current -1 a i ih high level input current 1 a cmos digital outputs v ol low level output voltage (4 ma load) 0.15 v v oh high level output voltage (4 ma load) vdd to 0.15 v table 36. i 2 c timing characteristics symbol parameter minimum maximum unit f scl scl clock frequency 100 400 khz tbuf bus free time between a stop and a start 1.3 ns thd;sta hold time for a repeated start 0.6 s tlow low period of scl 1.3 s thigh high period of scl 0.6 s tsu;sta set-up time for a repeated start 0.6 s thd;dat data hold time 300 ns tsu;dat data set-up time 100 ns tr rise time of scl, sda 20+0.1 cb 300 ns
doc id 022952 rev 2 63/88 VD5377 electrical characteristics figure 27. i 2 c timing characteristics tf fall time of scl, sda 20+0.1 cb 300 ns tsu;sto set-up time for a stop 0.6 s cb capacitive load of each bus line (scl, sda) - 400 pf table 36. i 2 c timing characteristics (continued) symbol parameter minimum maximum unit sda scl thd;sta tr thigh tf tsu;dat thd;dat tsu;sta tsu;sto ... ... thd;sta tlow tbuf stop start stop start all values referred to the minimum input level (high) = 0.7 vdd, and maximum input level (low) = 0.3 vdd
i 2 c interface VD5377 64/88 doc id 022952 rev 2 11 i 2 c interface the interface is 400 khz i 2 c, with very fast po lling rate for high cpi applications (down to 1ms period). 11.1 protocol figure 28. serial interface data transfer protocol 11.2 data format information is packed in 8-bi t packets (bytes) always followed by an acknowledge bit. the internal data is produced by sampling sda at a rising edge of scl. the external data must be stable during the high period of scl. the ex ceptions to this are start (s) or stop (p) conditions when sda falls or rise s respectively, while scl is high. the first byte contains the device address byte which includes the data direction read (r), ~write (w ), bit. figure 29. VD5377 serial interface address the byte following the address byte contains th e address of the first data byte (also referred to as the index). 12 7 8 a start condition stop condition sda scl acknowledge p s 3 4 56 address or data byte msb lsb 1 0 1 0 0 1 1 r/w
doc id 022952 rev 2 65/88 VD5377 i 2 c interface 11.3 message interpretation all serial interface communications with the sensor must begin with a start condition. if the start condition is followed by a valid address byte then further communications can take place. the sensor acknowledges the receipt of a valid address by driving the sda wire low. the state of the read/~write bit (lsb of the addres s byte) is stored and the next byte of data, sampled from sda, can be interpreted. during a write sequence the second byte received is an address index and is used to point to one of the internal registers. the serial interface automatically increments the index address by one location after each slave ackn owledge. the master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start, (sr). as data is received by the slave it is written bit by bit to a serial/parallel register. after each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. during a read message, the content of the addre ssed register is then parallel loaded into the serial/parallel register and clocked out of the device by scl. at the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge (nack) after reading a complete byte during a read operation. 11.4 type of messages 11.4.1 single location, single data write when a random value is written to the sensor, the message appears as shown in figure 30 . figure 30. single loca tion, single write the r/w bit is set to zero for writing. the writ e message is terminated with a stop condition from the master. 11.4.2 single location read when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written fi rst, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial bus to another master a repeated start condition is set between the write and read messages. in the example in figure 31 , the x motion vector scaling value (index 0x2a) is read. s a6 h a 07 h a 00 h a p start device ack address index data stop master slave
i 2 c interface VD5377 66/88 doc id 022952 rev 2 figure 31. single read as mentioned in the previous example, th e read message is terminated with a negative acknowledge (a ) from the master. 11.4.3 multiple location write it is possible to write data byte s to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. note: an auto-increment write is assumed if no stop condition occurs. figure 32. multiple location write 11.4.4 multiple location read multiple locations can be read within a single read messa ge. an auto-increment write is assumed. note: registers are read until the master nacks the data. figure 33. multiple location read: reading motion note: when reading x/y motion data a multiple read must be performed. s a sr a a a6 h 2a h a7 h 16 no data write read data from the master nack p a master slave sa 11a aa a6 h 07 h c1 incremental write p data written @ index = 08 data written @ index = 07 master slave incremental read saa a6 h 21 h sr x motion y motion no data write aa p a a7 h master slave
doc id 022952 rev 2 67/88 VD5377 i 2 c register map 12 i 2 c register map table 38 contains a subset of device registers which may be required by the end user. note: register addresses and default values are in hexadecimal. the ?default? column refers to the power-on register values in software standby before user initialization. the register type definitions are summarized in table 37 . table 37. register types type description pr hardware read only register prw hardware read/write register prwc hardware read/write register with auto set/clear r firmware read register rw firmware read/write register table 38. i 2 c register map addr (hex) register name signal name bit type default (hex) comment 0 major_revision major_revision 7:0 pr 01 major hardware revision number. updated in case of full mask regeneration. 0 = rev 1.x 1 = rev 2.x 2 = rev 3.x x = minor revision 1 minor_revision minor_revision 7:0 rw 00 minor hardware revision number. updated in case of metal fix and or rom changes. 0 = rev 0 1 = rev 1 2 = rev 2 2 analog_ctrl1 reserved 0 prw 01 reserved osc_48mhz_sel 2:1 prw 02 oscillator 48 mhz center frequency select. 0 = center freq = 34 mhz 1 = center freq = 39 mhz 2 = center freq = 44 mhz 3 = center freq = 48 mhz reserved 3 prw 00 reserved reserved 4 prw 01 reserved reserved 7:5 prw 00 reserved
i 2 c register map VD5377 68/88 doc id 022952 rev 2 3 analog_ctrl2 led_out_dmib_ctrl 0 prw 00 select the source of led out. 0 = auto (by dmib controller) 1 = manual (by led_out_manual) - for led test purposes only. led_out_manual 1 prw 00 if led_out_dmib_ctrl is high, defines the state of led_out. 0 = led driver disable (in manual mode) 1 = led driver enable (in manual mode) (for led test purposes only) dmib_dac_vref 3:2 prw 01 vref select for dmib dac 0 = 1v45 1 = 1v5 (default) 2 = 1v55 3 = 1v6 (recommended) led_dac_control 6:4 prw 07 adjust led drive dac drive output current. 0 = iout = 0 ma 1 = iout = 2.0 ma 2 = iout = 4.0 ma 3 = iout = 6.0 ma 4 = iout = 8.0 ma 5 = iout = 10.0 ma 6 = iout = 12.0 ma 7 = iout = 14.0 ma (default) led_out_polarity 7 prw 01 led_out_en polarity 0 = high when led must be on 1 = low when led must be on table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 69/88 VD5377 i 2 c register map 5 system_config automatic_power_ mode 0prw 01 power mode scheme 0 = manual 1 = automatic motion_pin_polarity 2 prw 00 motion pin polarity (in non idle system state) 0 = motion pin low when motion detected 1 = motion pin high when motion detected host_config_done 3 prw 00 bit needs to be set by host when configured after power up. use_standby_pin 4 prw 01 standby pin is used as chip select to enable i 2 c in auto power mode and standby pin is used to wake up the osc/dvreg (in sleep states in auto power mode). 0 = standby pin not used 1 = standby pin is used system_state 7:5 rw 01 legacy register - please use system_state (0x91) instead. 6 gpio_i2csel0 gpio_i2csel0_en 0 prw 01 i2csel0 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_i2csel0_a 1 prw 00 i2csel0 data output (when _en = 0) gpio_i2csel0_zi 2 pr 00 i2csel0 io value gpio_i2csel0_pd 3 prw 00 i2csel0 pull-down control (internal 35 kohms pull-down resistor) - active low 0 = io is pulled down 1 = io not pulled down table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 70/88 doc id 022952 rev 2 7 gpio_i2csel1 gpio_i2csel1_en 0 prw 01 i2csel1 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_i2csel1_a 1 prw 00 i2csel1 data output (when _en = 0) gpio_i2csel1_zi 2 pr 00 i2csel1 io value gpio_i2csel1_pd 3 prw 00 i2csel1 pull-down control (internal 35 kohms pull-down resistor) - active low 0 = io is pulled down 1 = io not pulled down 8 gpio_i2csel2 gpio_i2csel2_en 0 prw 01 i2csel2 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_i2csel2_a 1 prw 00 i2csel2 data output (when _en = 0) gpio_i2csel2_zi 2 pr 00 i2csel2 io value gpio_i2csel2_pd 3 prw 00 i2csel2 pull-down control (internal 35 kohms pull-down resistor) - active low 0 = io is pulled down 1 = io not pulled down 9 gpio_backled0 gpio_backled0_en 0 prw 00 backled0 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_backled0_a 1 prw 01 backled0 data output (when _en = 0) gpio_backled0_zi 2 pr 0 1 backled0 io value gpio_backled0_tm 3 prw 00 reserved. do not modify this bit. gpio_backled0_a_ctrl 4 prw 00 backled0 data output origin 0 = output value from hw register 1 = output value from pwm 0 gpio_backled0_ opendrain 7prw 01 backled0 pad open drain control 0 = backled0 pad normal config 1 = backled0 pad in open drain (a=en) table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 71/88 VD5377 i 2 c register map a gpio_backled1 gpio_backled1_en 0 prw 00 backled1 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_backled1_a 1 prw 01 backled1 data output (when _en = 0) gpio_backled1_zi 2 pr 0 1 backled1 io value gpio_backled1_tm 3 prw 00 reserved. do not modify this bit. gpio_backled1_a_ctrl 4 prw 00 backled1 data output origin 0 = output value from hw register 1 = output value from pwm 1 gpio_backled1_ opendrain 7prw 01 backled1 pad open drain control 0 = backled1 pad normal config 1 = backled1 pad in open drain (a=en) b gpio_backled2 gpio_backled2_en 0 prw 00 backled2 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_backled2_a 1 prw 01 backled2 data output (when _en = 0) gpio_backled2_zi 2 pr 0 1 backled2 io value gpio_backled2_tm 3 prw 00 reserved. do not modify this bit. gpio_backled2_a_ctrl 4 prw 00 backled2 data output origin 0 = output value from hw register 1 = output value from pwm 2 gpio_backled2_ opendrain 7prw 01 backled2 pad open drain control 0 = backled2 pad normal config 1 = backled2 pad in open drain (a=en) table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 72/88 doc id 022952 rev 2 c gpio_motion gpio_motion_en 0 prw 00 motion output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_motion_a 1 prw 01 motion data output (when _en = 0) gpio_motion_zi 2 pr 01 motion io value gpio_motion_pd 3 prw 01 motion pull-down control (internal 35 kohms pull-down resistor) - active low 0 = io is pulled down 1 = io not pulled down gpio_motion_a_ctrl 4 prw 00 motion data output origin 0 = output value from hw register 1 = output value from motion detect ip reserved 6:5 prw 02 reserved gpio_motion_ opendrain 7prw 00 motion pad open drain control 0 = motion pad normal config 1 = motion pad in open drain (a=en) d gpio_gpio0 gpio_gpio0_en 0 prw 00 gpio0 output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_gpio0_a 1 prw 00 gpio0 data output (when _en = 0) gpio_gpio0_zi 2 pr 00 gpio0 io value gpio_gpio0_a_ctrl 4 prw 00 gpio0 data output select, either as led_out_en or from register bank. 0 = output value from hw register 1 = led_out_en (polarity set in register 0x3 analog_ctrl2 bit 7) gpio_gpio0_ opendrain 7prw 00 gpio0 pad open drain control 0 = gpio0 pad normal config 1 = gpio0 pad in open drain (a=en) table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 73/88 VD5377 i 2 c register map e gpio_standby gpio_standby_en 0 prw 01 standby output enable (active low) 0 = pad configured as output 1 = pad configured as input gpio_standby_a 1 prw 00 standby data output (when _en = 0) gpio_standby_zi 2 pr 00 standby io value f pwm_period pwm_period 7:0 prw ff pwm period duration (20us tick period) 10 pwm_pulsehigh0 pwm_pulse_high0 7:0 prw 00 pwm0 pulse high duration (20 us tick period) - 0 = disable 11 pwm_pulsehigh1 pwm_pulse_high1 7:0 prw 00 pwm1 pulse high duration (20 us tick period) - 0 = disable 12 pwm_pulsehigh2 pwm_pulse_high2 7:0 prw 00 pwm2 pulse high duration (20 us tick period) - 0 = disable 15 clocks_lo clk_motion_timer 1 prw 00 timer clock enabled (forced always on) clk_pci_en 4 prw 00 pci clock enable (forced always on) clk_framedump_en 5 prw 00 framedump clock enable (forced always on) 16 resets software_reset_n 0 prwc 01 software reset re sult in full system reboot (active low - auto cleared) reserved 4:1 prw 0f do not modify these bits. framedump_reset_n 5 prw 00 framedump reset signal (active low) reserved 7:6 prw 00 do not modify these bits. 19 control motion_engine_start 7 prw 00 timer interrupt enable. this enables the motion timer to operate. motion timer generates pulses that trigger frame capture and motion processing. table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 74/88 doc id 022952 rev 2 1c frame_rate_ control frame_rate_sel 2:0 prw 02 frame rate selection (value for internal osc running @48mhz) 0 = 0.5 kf/s (2 ms period) 1 = 1 kf/s (1 ms period) 2 = 2 kf/s (500 us period) 3 = 2.5 kf/s (400 us period) 4 = 2.9 kf/s (350 us period) 5 = 3.3 kf/s (300 us period) 6 = 3.6 kf/s (275 us period) 7 = 4 kf/s (250 us period) frame_rate_ctrl 4 rw 00 frame rate management control 0 = automatic (1k/2 k/max f/s auto frame rate) 1 = manual (set with frame_rate_sel reg) max_auto_frame_ rate 7:5 rw 05 maximum frame rate to be applied in auto frame rate mode 0 = not allowed 1 = not allowed 2 = 2 kf/s (500 us period) 3 = 2.5 kf/s (400 us period) 4 = 2.9 kf/s (350 us period) 5 = 3.3 kf/s (300 us period) 6 = 3.6 kf/s (275 us period) 7 = 4 kf/s (250 us period) 21 x_motion x_motion 7:0 pr 00 x motion data since last polling was done. note that the internal accumulator is reduced from this value every time it is read. 22 y_motion y_motion 7:0 pr 00 y motion data since last polling was done. note that the internal accumulator is reduced from this value every time it is read. table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 75/88 VD5377 i 2 c register map 23 overflow x_overflow 0 pr 00 this register records if the x- motion integrator has reached its limit. 0 = no overflow 1 = overflow y_overflow 1 pr 00 this register records if the y- motion integrator has reached its limit. 0 = no overflow 1 = overflow reserved 2 pr 00 reserved no_motion 3 pr 01 this bit is asserted as long as both x/y integrators are empty (logical or between motion_w and motion_y). 0 = motion 1 = no motion motion_acc_flush_en 5 prwc 00 if set this bit flushes the motion accumulators (self cleared). adapt_cpi_en 6 rw 00 if set the cpi is function of the detected motion 0 = no adaptive cpi 1 = enable adaptive cpi reserved 7 prw 00 reserved 27 parameters_2 invert_x 0 prw 00 allows x to be inverted invert_y 1 prw 00 allows y to be inverted reserved 2 prw 00 reserved swap_xy 3 prw 01 replaces x with y and y with x. test_pattern_en 5 prw 00 test pattern enable 0 = normal vector from motion detector 1 = diamond shape vector test pattern test_pattern_speed 7:6 prw 00 test pattern enable 0 = |motion| = 127 maximum speed 1 = |motion| = 64 2 = |motion| = 32 3 = |motion| = 16 table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 76/88 doc id 022952 rev 2 28 parameters_3 reserved 3:0 prw 04 reserved reserved 4 prw 01 reserved hpf_5x5_sel 5 prw 00 select between 3 x 3 and 5 x 5 high pass filter 0 = 3 x 3 high pass filter 1 = 5 x 5 high pass filter reserved 6 prw 01 reserved 29 min_features min_features 7:0 prw 10 this register represents the minimum feature count below which motion is inhibited. multiply by 16 to get the actual feature count thre shold. default is 16d = 256. 2a x_scaling motion_x_scaling 7:0 prw 10 scaling for x motion vectors. resolution is calculated as register value x 100 x m, where m is the lens magnification. so, for m = 0.5: 0x08 = 400 cpi that is 8 x 100 x 0.5 0x0c = 600 cpi that is 12 x 100 x 0.5 2b y_scaling motion_y_scaling 7:0 prw 10 scaling for y motion vectors. resolution is calculated as register value x 100 x m, where m is the lens magnification. so, for m = 0.5: 0x08 = 400 cpi that is 8 x 100 x 0.5 0x0c = 600 cpi that is 12 x 100 x 0.5 2c frame_average frame_avg 7:0 pr 00 frame average calculated over a 16 x 16 centered window. possibly useful for production test. 2f max_abs_motion max_abs_motion 6:0 pr 00 max(abs(x motion), abs(y motion)) either from integrated or instant motion. 31 features features_report 7:0 pr 00 feature count report, as the sum of absolute differences between pixels and the field average. bits [11:4] are represented here so x16 to calculate the actual feature count. maximum value is 4080 = 255 x 16. table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 77/88 VD5377 i 2 c register map 35 adaptcpi_min_ motion adaptcpi_min_motion 7:0 prw 10 minimum value of max(|x frame motion|, |y frame motion|) from which the cpi is adaptive (if feature enabled). 36 adaptcpi_min_ scaling adaptcpi_min_scaling 7:0 prw 08 minimum motion scaling value when adaptive cpi feature is enabled. 37 adaptcpi_range s adaptcpi_log_ motion_range 2:0 prw 05 log value of motion range from which the cpi is adaptive (that is max motion = min + 2^adaptcpi_log_motion_range). 0 = motion range = 1 1 = motion range = 2 2 = motion range = 4 3 = motion range = 8 4 = motion range = 16 5 = motion range = 32 6 = motion range = 64 7 = motion range = 128 adaptcpi_log_ scaling_range 6:4 prw 04 log value of motion scaling range from which the cpi is adaptive (that is max scaling = min + 2^adaptcpi_log_scaling_range). 0 = scaling range = 1 1 = scaling range = 2 2 = scaling range = 4 3 = scaling range = 8 4 = scaling range = 16 5 = scaling range = 32 6 = scaling range = 64 7 = scaling range = 128 reserved 7 pr 01 reserved table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 78/88 doc id 022952 rev 2 43 exposure_ control autoexpo_en 0 rw 01 auto exposure control 0 = disable 1 = enable autoexpo_status 6:4 r 00 auto exposure status 0 = undef (no aec performed yet) 1 = low (exposure increasing) 2 = stable (max exp pix within range) 3 = high (exposure decreasing) 4 = saturated (exposure saturation decreasing) autoexpo_limit_flag 7 r 00 exposure limit reached flag 0 = exposure time within range 1 = exposure time limit reached 44 max_expo_pix max_exposed_pixel_ value 7:0 pr 00 second maximum pixel value of the current frame (before cds) 45 max_expo_pix_ thresh_high max_exposed_pixel_ thresh_high 7:0 rw f0 high threshold value of max exposed pixel where the aec is stable. 46 max_expo_pix_ thresh_low max_exposed_pixel_ thresh_low 7:0 rw b4 low threshold value of max exposed pixel where the aec is stable. 47 expotime exposure_time 7:0 prw 40 exposure time value in 3mhz clk period step (333ns) 49 expotime_max exposure_time_max 7:0 rw ff maximum exposure time applied by the aec. 4a expotime_min exposure_time_min 7:0 rw 01 minimum exposure time applied by the aec. 4b expo_frame_ update autoexpo_frame_ update 7:0 rw 01 exposure update frequency (every n + 1 frames). default is every two frames. 4e expotime_inc_ step expo_inc_step 7:0 rw 04 exposure increment step (used when below max_expo_pix_thresh_low) 4f expotime_dec_ step expo_dec_step 7:0 rw 04 exposure decrement step (used when above max_expo_pix_thresh_high) 50 expotime_sat_ dec_step expo_sat_dec_step 7:0 rw 10 exposure decrement step (used when above max_expo_pix is saturated = 255) table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 79/88 VD5377 i 2 c register map 51 control dmib_ctrl_mode 0 rw 00 dmib controller timing switch mode 0 = manual (chosen by dmib_timing reg) 1 = automatic (system auto sets the dmib_timing mode, status reported in dmib_timing reg) dmib_timing 1 prw 00 dmib controller timing mode 0 = normal dmib timing (same as 376 with double expo time possible) 1 = sunlight dmib timing reserved 7 prw 00 reserved 56 cdsout_sel cds_out_sel 1:0 prw 00 selects what is output from the dmib controller (going to motion engine and or video output data). 0 = cds frame 2 = exposed frame 3 = black frame reserved 4 prw 00 reserved 58 framedump_ pixdata framedump_pixdata 7:0 pr 00 pixel data in frame dump mode, automatically incremented to next pixel after a read of this register. 59 framedump_ctrl framedump_en 0 prw 00 frame dump mode enable 0 = disable 1 = enable framedump_start 1 pr 00 frame dump started framedump_ready 2 pr 00 flag set when a frame is ready to be read by host, pixel[0] is ready in register framedump_pixdata. framedump_done 3 pr 00 flag set when a complete frame (400 pixels) has been read. pci_test_enable 4 prw 00 muxed pci data onto pads (2 bits nibble + fst + qclk) 0 = disable 1 = enable framedump_mire 7 prw 00 in frame dump mode outputs a grey scale image (pixel_counter). table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 80/88 doc id 022952 rev 2 7c devaddr i2cs_index_auto_inc_ en 0 prw 01 auto increment function i2cs_dev_addr 7:1 prw 53 i 2 c device address 80 fw_top_revision ucfwtoprevision 7:0 rw 20 system level firmware revision 81 personal_ config ucpersonalconfig 7:0 rw 00 result of the i2c_sel[20] pad decoding done at start-up. 0 = i2c device address = 0xa6 + config 0 1 = i2c device address = 0xa6 (reserved) 2 = i2c device address = 0xc6 + config 2 3 = i2c device address = 0xd6 + config 3 4 = i2c device address = 0xe6 + config 4 5 = i2c device address = 0x36 + config 5 6 = i2c device address = 0x46 + config 6 7 = i2c device address = 0x20 + config 7 82 power_mode_ control reserved 1:0 00 do not modify these bits. ucnbsleepstate 5:4 rw 03 in automatic power mode, number of sleep states. table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 81/88 VD5377 i 2 c register map 83 backlight_ control bbacklightenable 0 rw 00 backled pwm enable 0 = disable 1 = enable bsinglebackled 1 rw 00 single backled scheme control par pwm0 only 0 = three independent backleds 1 = backled controlled by pwm 0 bpwmpolarity 2 rw 00 backled pwm signal polarity 0 = high when led must be on (= pwm0) 1 = low when led must be on (= !pwm0) bbackledgaterenable 3 rw 00 enable the gating of backled pwm signal with dmib gater signal. 0 = disable 1 = enable bpwmholdenable 4 rw 00 enable the hold mechanism when dmib gater signal is on. 0 = disable 1 = enable bbacklightreset 7 rwc 00 in sw stby reset the control of backlight control (self cleared). 0 = disable 1 = enable 84 auto_running_ timeout_hi uwrunningtimeout 15:0 rw 00 in running state, time to enter sleep1 state when no motion is detected. expressed in number of frames, for example, in automatic frame rate = step of 1 ms (1 kf/s), for fixed frame rate depending on the chosen frame rate. 85 auto_running_ timeout_lo 32 86 auto_sleep1_ timeout_hi uwsleep1timeout 15:0 rw 03 in sleep1 state, time to enter sleep2 state when no motion is detected. expressed in number of frames, for example, step of sleep1 latency. 87 auto_sleep1_ timeout_lo 20 88 auto_sleep2_ timeout_hi uwsleep2timeout 15:0 rw 17 in sleep2 state, time to enter sleep3 state when no motion is detected. expressed in number of frames, for example, step of sleep2 latency. 89 auto_sleep2_ timeout_lo 70 table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 82/88 doc id 022952 rev 2 8a auto_sleep1_ latency ucsleep1latency 7:0 rw 05 maximum latency to wake up the system in sleep1 state. corresponds to the time between two wake-up periods (a wake-up period corresponds to a single frame motion detection processing). 0 = 400 us 1 = 1 ms 2 = 1.4 ms 3 = 2 ms 4 = 4 ms 5 = 10 ms 6 = 20 ms 7 = 50 ms 8 = 100 ms 9 = 150 ms 10 = 200 ms 11 = 500 ms 12 = 1 s 13 = 1.5 s 14 = 2 s 15 = 2.6 s 8b auto_sleep2_ latency ucsleep2latency 7:0 rw 08 maximum latency to wake up the system in sleep2 state. corresponds to the time between two wake-up periods (a wake-up period corresponds to a single frame motion detection processing). 0 = 400 us 1 = 1 ms 2 = 1.4 ms 3 = 2 ms 4 = 4 ms 5 = 10 ms 6 = 20 ms 7 = 50 ms 8 = 100 ms 9 = 150 ms 10 = 200 ms 11 = 500 ms 12 = 1 s 13 = 1.5 s 14 = 2 s 15 = 2.6 s table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 83/88 VD5377 i 2 c register map 8c auto_sleep3_ latency ucsleep3latency 7:0 rw 0b maximum latency to wake up the system in sleep3 state. corresponds to the time between two wake-up periods (a wake-up period corresponds to a single frame motion detection processing). 0 = 400 us 1 = 1 ms 2 = 1.4 ms 3 = 2 ms 4 = 4 ms 5 = 10 ms 6 = 20 ms 7 = 50 ms 8 = 100 ms 9 = 150 ms 10 = 200 ms 11 = 500 ms 12 = 1 s 13 = 1.5 s 14 = 2 s 15 = 2.6 s 8d auto_movement_ ctrl1 bautomovefilterenab le 0rw 00 auto movement filter enable 0 = disable 1 = enable ucautomovefilterfra menb 6:1 rw 07 number of frames on which the auto movement filter is applied (must be greater than 1). bautomovesaturated expo 7rw 00 when image in high light and exposure (reg 0x47) is set to 1, flag used by engine to discard motion in this condition. 0 = disable 1 = enable table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
i 2 c register map VD5377 84/88 doc id 022952 rev 2 8e auto_movement_ ctrl2 ucautomovefilterlate ncy 3:0 rw 01 latency between frames on which the auto movement filter is applied. 0 = 400 us 1 = 1 ms 2 = 1.4 ms 3 = 2 ms 4 = 4 ms 5 = 10 ms 6 = 20 ms 7 = 50 ms 8 = 100 ms 9 = 150 ms 10 = 200 ms 11 = 500 ms 12 = 1 s 13 = 1.5 s 14 = 2 s 15 = 2.6 s ucautomovefilterloo p 7:4 rw 03 set the number of sequences to detect motion to grant motion in sleep mode. 90 device_id ucdeviceid 7:0 rw 4d device id 0 = vd5376 (and previous) 77 = VD5377 91 system_state ucsystemstate 2:0 rw 01 s377 system state 0 = boot 1 = software standby 2 = autorunning 3 = sleep_1 4 = sleep_2 5 = sleep_3 6 = manualrunning table 38. i 2 c register map (continued) addr (hex) register name signal name bit type default (hex) comment
doc id 022952 rev 2 85/88 VD5377 acronyms and abbreviations 13 acronyms and abbreviations table 39. acronyms and abbreviations acronym/abbrevia tion definition abs absolute (value) acc accumulator ack acknowledge aec automatic exposure control amf auto-movement filter ofn optical finger navigation cds correlated double sampling cpi counts per inch cpu central processing unit dac digital-to-analog converter dmib digital mouse imaging block dpi dots per inch dsl direct sunlight f/s frames per second gpio general purpose input/output ic integrated circuit i 2 c inter integrated circuit led light emitting diode m magnification mcu micro controller unit mep maximum exposed pixel msb most significant bit nack negative acknowledge osc oscillator por power-on reset pwm pulse width modulation ri relative illumination rom read only memory sad sum of absolute differences scl i 2 c serial clock sda i 2 c serial data
ordering information VD5377 86/88 doc id 022952 rev 2 14 ordering information VD5377 silicon is current ly available in the formats listed in table 40 . more detailed information is available on request. table 40. delivery formats order code description thickness VD5377/uw unsawn wafer 725 m VD5377cb/uw unsawn wafer 180 m VD5377cb/sw sawn wafer 180 m VD5377cb/gp gel pack (evaluation samples only, maximum quantity 500) 180 m
doc id 022952 rev 2 87/88 VD5377 revision history 15 revision history table 41. document revision history date revision changes 23-mar-2012 1 initial release 07-feb-2013 2 minor updates throughout.
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